1. Field of the Invention
The present invention relates to the field of failure analysis of integrated circuits.
2. Prior Art
In order to evaluate failed semiconductor integrated circuits, various well known failure analysis techniques require the removal of passivation layers in order to expose the underlying circuit layers. The passivation layer or layers are removed so that probing of the integrated circuit can be achieved. Analysis of failed semiconductor devices is essential in order to determine the cause of such failure.
Once failure has been detected, the integrated circuit which is typically embodied in a die is exposed. Normally, this entails removing a portion of the outer packaging material to expose the die, although the die can be completely removed from the package. In certain instances, where a lid is placed over the die during formation of the package, only the lid need be removed to expose the die.
After exposing the die, etching methods are used to remove the protective passivation layers overlying the circuit layers. The circuit components are embedded in the lower layers of the substrate and are interconnected by interconnection layers, which are typically of metal. The passivation layer is usually comprised of glass, such as phosphosilicate glass. Although wet etching can be used, the wet etchant technique is not preferable for use with other passivation layers because wet etching techniques will destroy the metal bond pads before complete etching can be achieved. Therefore, where the passivation layer is comprised of oxide, nitride or oxynitride layers, plasma etching techniques utilizing fluorocarbons are typically used. Plasma etching will not deteriorate the metal layers as is the case with the wet etching technique.
However, problems are still encountered in the use of plasma etching to remove the passivation layers to expose the underlying metal layers. For example, without the use of selective etching techniques, isotropic etching will tend to etch layers underlying the metal layers. That is, because isotropic etching techniques etch away the material in all directions, and in many instances, insulating layers underlying metal areas are also etched away. Without the underlying support, the metal lines are simply lifted away.
In order to provide selective etching, anisotropic etching techniques are used to prevent the underlying layers from being etched away. Unfortunately, most anisotropic plasma etching techniques cause sputtering to occur. Sputtering is a phenomena well-known in the prior art and is simply stated as the emission of secondary material caused by the bombardment of particles used for plasma etching. For example, unwanted sputtering of metal particles onto the passivation layer occurs during anisotropic plasma etching, such sputtering of metal originating either from the metal areas of the chip, or from the metallic base upon which the die is located. The metallic base, typically a preform, is usually comprised of gold. Metal is sputtered onto portions of the passivation layer such that the sputtered metal landing on the passivation layer inhibits etching of the underlying passivation layer, the result being a non-uniform topography of the layer being etched. Additionally, the gas mixture used for plasma etching has a tendency to form polymers. The formation of the polymers on the etching surface can produce a Teflon.TM.- like compound which also inhibits the etching of the underlying surface.
It is appreciated that what is needed is an etching technique that removes protective passivation layers of the integrated circuit device to expose the various underlying metal areas, but that the removal of the passivation layers be achieved in a selective and uniform manner to expose the metal areas without destroying it. Although various prior art techniques are known to remove passivation layers using anisotropic etching, sputtering and polymerization present significant problems in removing the passivation layer.